// `timescale 1ns/1ns
module encode_input_generate(key1,key2,key3,original_in,original_clk,rstn);
//本模块是产生 编码模块需要的输入数据的
input key1,key2,key3;
input rstn,original_clk;
output [8:0] original_in;

wire key1,key2,key3;
wire rstn,original_clk;
wire [8:0] original_in;
//----------------------------------------------------------
//随机模式

reg cnt0;
reg [7:0] cnt1;
assign original_in[8:0] = {cnt0,cnt1[7:0]};
always@(posedge original_clk or negedge rstn)begin
	if(!rstn)cnt1 <= 0;
	else begin
		if(!key2) 
		cnt1 <= cnt1+1'b1;
	end
end

//key3用于 标记 特殊值
always@(posedge key3 or negedge rstn)begin
if(!rstn)cnt0 <= 0;
	else begin
	cnt0 <= !cnt0;
	end
end

//----------------------------------------------------------
//按键输入模式
/*
reg [3:0] cnt1;
reg [3:0] cnt0;
// cnt0为低四位输入,cnt1为高四位输入
assign original_in = {cnt1,cnt0};

// key3控制低4位输入
always@(posedge key3 or negedge rstn)begin
	if(!rstn)
		cnt0 <= 0;
	else
		cnt0 = cnt0+1'b1;
	
end

always@(posedge key2 or negedge rstn)begin
	if(!rstn)
		cnt1 <= 0;
	else
		cnt1 = cnt1+1'b1;
	
end
*/

//----------------------------------------------------------
/*
//计数输入模式

reg [7:0] cnt8b;
reg i,j;
assign original_in = {1'b0,cnt8b};
always@(posedge key2 or negedge rstn)begin
	if(!rstn)
		i <= 0;
	else 
		i = 1;
		
end

always@(posedge key3 or negedge rstn)begin
	if(!rstn)
		j <= 0;
	else 
		j = 1;
		
end
// assign cnt8b = i? cnt8b + 1'b1:cnt8b;
// assign cnt8b = j? cnt8b - 1'b1:cnt8b;

always@(i or j)begin
	if(!rstn)
		cnt8b <= 0;
	else begin 
		if(i) cnt8b <= cnt8b + 1'b1;
		else if(j) cnt8b <= cnt8b - 1'b1;
		else;
	end	
end

//----------------------------------------------------------
*/
endmodule
